1. Field of the Invention
The present invention relates to random access memory circuits and, in particular, to a small, high speed multi-port memory cell that utilizes all CMOS transistors, transfers data differentially and can be easily modified to accommodate additional ports.
2. Discussion of the Prior Art
A memory cell is an electronic circuit in which a binary digit, or bit, of information can be stored. In an integrated circuit memory device, a large number of memory cells are arranged in matrix form to provide storage capability for large volumes of binary data. In addition to the memory cell storage matrix, the memory device includes a write port for writing binary data into the memory cells and a read port for reading stored binary data from the memory cells.
It is often useful to provide a memory cell with multiple write and read ports, all independent of each other. This multi-port architecture permits simultaneous access to more than one memory cell or groups of memory cells in the storage matrix, thereby improving access to data and decreasing the time required for operations relating to that data.
FIG. 1 shows a typical prior art multi-port memory cell 10 that is implemented with bipolar transistors in an ECL (emitter-coupled logic) circuit. NPN transistors 12 and 14 form a flip-flop that stores data, with stand-by current supplied through resistors 16 and 18 from a voltage source V.sub.REF. Write and read operations are accomplished by steering current through differentially connected NPN transistors 20,22,24,26. During a write operation, transistors 20 and 22 are enabled by current applied to their emitter regions via the WRITE ROW line. One of the transistors 20,22 turns on, depending on the state of the complementary DATA IN lines, each of which is connected to the base of one of the transistors 20,22, and diverts the stand-by current, thus writing data to the memory cell 10. The read circuitry includes transistors 24 and 26 which form a differential cascode sensing circuit in combination with a sense amplifier (not shown) that drives the complementary DATA OUT lines and the collectors of transistors 24 and 26 to a relatively constant voltage. During a read operation, transistors 24 and 26 are enabled by current applied to their emitter regions via the READ ROW line, turning one of the transistors on, depending on the state of the memory cell storage nodes A and B. The sense amplifier senses differential current flowing through the DATA OUT lines via transistors 24 and 26.
It should be apparent to those familiar with the art that additional write ports can readily be added to memory cell 10 by adding additional WRITE lines and associated NPN transistor pairs with collectors connected to the storage nodes A and B. Similarly, additional read ports can be provided by adding READ lines and associated NPN transistor pairs with their bases connected to nodes A and B.
Although memory cell 10 is a high speed circuit due to its ECL circuitry, it requires substantial power both to retain the data in the memory cell during standby and for read and write operations. It also requires a relatively large layout area.
FIG. 2 shows another prior art memory cell 30 that adds two bipolar transistors 44 and 46 to a conventional, single-port, six-transistor (6T) complementary metal-oxide semiconductor (CMOS) memory cell to provide a multi-port architecture. The basic 6T CMOS memory cell includes a CMOS flip-flop formed by two cross-coupled pairs of complementary MOSFET transistors 32,34 and 36,38 that are interconnected to provide complementary data storage nodes A and B. Writing to the memory cell 30 is accomplished by enabling the WRITE ROW line, which turns on n-channel transistors 40 and 42, thereby writing the data on the complementary DATA IN lines to the storage nodes A and B. Reading from the memory cell 30 is accomplished via the two bipolar NPN transistors 44 and 46, one of which turns on, based on the state of the storage nodes A and B, to drive its corresponding DATA OUT line when the READ ROW is enabled.
In several respects, the memory cell 30 shown in FIG. 2 is an improvement over the FIG. 1 memory cell 10. Memory cell 30 reduces the amount of current required to store data because the CMOS flip-flop requires only small junction leakage current to retain its state. As with the FIG. 1 cell, additional ports can easily be added.
However, although cell 30 has a high speed read path, using inherently fast bipolar transistors to drive the DATA OUT lines, the read operation is slowed because of the large (600-800 mv) swing on the DATA OUT lines and the large READ ROW line capacitance. In addition, incorporation of the bipolar transistors increases the layout area. The use of the bipolar devices also makes for difficulty in level matching of the eight devices utilized in the design. Because the READ ROW line swings by at least 600-800 mv, the voltage across the memory cell 30 at standby is less than the full supply; this increases the possibility of data upsets because of reduced noise immunity and increased sensitivity to alpha events.
A related memory cell 50, the so-called "Stanford cell" shown in FIG. 3, also utilizes the basic CMOS flip-flop storage cell structure (i.e., complementary transistors 32,34 and 36,38) of the FIG. 2 cell, but is single-ended via bipolar transistor 48 for read operations and via MOSFET transistor 50 for write operations. Although simpler than the FIG. 2 cell, memory cell 50 requires a reference for read operations and has poor common mode rejection of spurious signals. It also suffers from the disadvantages of difficult level matching and increased susceptibility to alpha upset due to use of the bipolar transistor 48.